Dynamic buffer management to improve the performance of fault tolerance adaptive Network-On-Chip applications

Abstract

Networks-On-Chip are developed with a trade-off between latency and power dissipation defined at design time. But, if the communication pattern is changed, decisions taken at design time (say buffer size) may result in large area and power consumption or higher latency. Using large buffers to guarantee performance leads to excessive power dissipation. Small buffers reduce power consumption but result in increase in latency. The purpose of the proposed work is to design a heterogeneous router where the buffer slots are dynamically assigned to improve the performance, under different communication needs in fault-tolerant adaptive NoC applications. In the proposed router, buffer slots can dynamically be re-allocated for various applications to improve performance. Reallocation is based on the number of hotspots using EBLA (Extended Buffer Loan Algorithm). By introducing oversized IPs (OIPs), regular mesh-based NoC architecture may be destroyed. Resulting mesh-based NoC becomes irregular and needs new routing algorithms to solve routing problems in case of faulty links. A NoC with irregular 2D mesh topology is considered and an fault tolerant adaptive routing algorithm is used.