Efficient design of Dual Digital Up Converter for WCDMA and CDMA2000 using system generator

Abstract

This paper presents an efficient method to design Dual Digital Up Converter (DUC) for WCDMA and CDMA2000 for Software Defined Radios (SDRs). The proposed Design which includes a programmable DDS, mixer and three cascaded stages of programmable digital filters has been simulated with Matlab, designed with Xilinx system generator and synthesized with Xilinx Synthesis Tool (XST) targeting Spartan 3A based xc3sd1800a FPGA. The Dual-mode feature is achieved by using a control unit which loads the filters coefficients of each system from ROM to the programmable digital filters upon desired System. The programmable DDS module is generated by Xilinx DDS Compiler and can operate at maximum frequency of 61.44MHz and provide the flexibility for multi-carrier base station. The results show that the system design flow based on Xilinx System Generator is simple and feasible and meets the performance requirements for the downlink transmit path for each system. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.