Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication

Abstract

The Affine Motion Estimation (AME) is a new and high-complexity task of the Versatile Video Coding (VVC) standard. The AME requires the Affine Motion Compensation (MC) to be performed for 4$\times$ 4 subblocks, where one among 156-tap interpolation filters was adopted to interpolate each sample of the 4$\times$ 4 subblock according to the motion vector relative to this subblock. This work presents two dedicated hardware implementations for the Affine MC of the VVC standard, the first focusing on the reduction of power dissipation and the second on the area requirement. The ASIC synthesis results of these architectures for TSMC 40nm standard cells show an area requirement of 54. 43k gates and power dissipation of 12. 8mW for the power efficient variant, while for the hardware efficient, the area requirement is 21. 91k gates and power dissipation of 14.41mW.