Real-Time Drowsiness Alert System from EEG Signal Based on FPGA

Abstract

Driver drowsiness is one of the major factors behind road accidents. Every year thousands of people lose their lives and property due to this problem. Proper solutions should be taken to minimize this incident. So far some methods have been developed for detecting drowsiness, but proper real-time detection remains a challenge. As a result, we are proposing an FPGA-based approach that can detect drowsiness from EEG signals within nanoseconds. To design the proposed system, the magnitude of the EEG signal frequency is estimated by using 128-FFT, then the data is observed sample by sample by the timing diagram for comparing the duration or distance to detect the existence of theta region equal to the threshold value. After detecting drowsiness, the system would trigger an alarm within nanoseconds to alert the user. As the system is designed on FPGA, it is dynamically adaptable and capable of parallel processing which gives a very fast response (12ns). This proposed system is designed on XILINX VIVADO software by using Verilog HDL language. The design has been simulated on the Artix-7 field-programmable gate array (FPGA) development board by the software. This design offers some outstanding features such as a memory capacity of only 11.32 MB, power consumption of 82.338 mW with low voltage, and current of 1.8V and 1.8mA respectively. The proposed system can be used in real-time drowsiness detection while playing a major role in avoiding road accidents considerably.