Correctness checking of HDL-model behavior based on runtime trace matching

Abstract

Correctness checking of HDL-model behavior is an integral part of runtime verification of hardware. As a rule, it is based on comparing of HDL-model behavior and reference model behavior, developed in high-level programming languages. Being verified, both models are stimulated with the same input sequence; their output traces are caught and matched. Due to the abstractness of the reference model, the matching is not a trivial task as event sequences can be different and some events of one trace may miss in the other one. A methodology of runtime trace matching for hardware models of different abstraction levels is suggested in this paper. The methodology has been successfully applied to a number of industrial projects of unit-level microprocessor verification.