D. Theodoropoulos, Nikolaos S. Alachiotis, D. Pnevmatikatos
{"title":"Multi-FPGA Evaluation Platform for Disaggregated Computing","authors":"D. Theodoropoulos, Nikolaos S. Alachiotis, D. Pnevmatikatos","doi":"10.1109/FCCM.2017.20","DOIUrl":null,"url":null,"abstract":"We present a versatile FPGA-based evaluation platformfor exploring alternative execution strategies on disaggregatedenvironments for applications, considering differentprocessing block types: compute cores, memory, and accelerators. Developers can interconnect different blocks types in orderto create optimal configurations. A user-level software libraryallows quick mapping of applications on real hardware. Wehave implemented a fully working prototype using three ZC706FPGA boards, and evaluated different software / hardwareconfigurations of a matrix multiplication benchmark.","PeriodicalId":124631,"journal":{"name":"2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FCCM.2017.20","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
We present a versatile FPGA-based evaluation platformfor exploring alternative execution strategies on disaggregatedenvironments for applications, considering differentprocessing block types: compute cores, memory, and accelerators. Developers can interconnect different blocks types in orderto create optimal configurations. A user-level software libraryallows quick mapping of applications on real hardware. Wehave implemented a fully working prototype using three ZC706FPGA boards, and evaluated different software / hardwareconfigurations of a matrix multiplication benchmark.