S.-D. Yin, Wenfei Hu, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Yan Wang
{"title":"An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental Learning","authors":"S.-D. Yin, Wenfei Hu, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Yan Wang","doi":"10.1109/asp-dac52403.2022.9712601","DOIUrl":null,"url":null,"abstract":"In this paper, we propose an efficient Kriging-based constrained multi-objective evolutionary algorithm for analog circuit synthesis via self-adaptive incremental learning. The incremental learning technique is introduced to reduce time complexity of training the Kriging model from $O(n^{3})$, to $O(n^{2})$, where $n$ is the number of training points. The proposed approach reduces the total optimization time in three aspects. First, by reusing the previously trained models, a self-adaptive incremental learning strategy is applied to reduce the training time of the Kriging model. Second, we use non-dominated sorting and modified crowding distance to prescreen the most promising one to be simulated, which largely reduce the number of simulations. Third, as there is no internal optimization, the prediction time of the Kriging model is saved. Experimental results on two real-world circuits demonstrate that compared with the state-of-the-art multi-objective Bayesian optimization, our method can reduce the training time of Kriging model by 95% and the prediction time by 99.7% without surrendering optimization results. Compared with NSGA-II and MOEA/D, the proposed method can achieve up to 10X speed up in terms of the total optimization time while achieving better results.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asp-dac52403.2022.9712601","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, we propose an efficient Kriging-based constrained multi-objective evolutionary algorithm for analog circuit synthesis via self-adaptive incremental learning. The incremental learning technique is introduced to reduce time complexity of training the Kriging model from $O(n^{3})$, to $O(n^{2})$, where $n$ is the number of training points. The proposed approach reduces the total optimization time in three aspects. First, by reusing the previously trained models, a self-adaptive incremental learning strategy is applied to reduce the training time of the Kriging model. Second, we use non-dominated sorting and modified crowding distance to prescreen the most promising one to be simulated, which largely reduce the number of simulations. Third, as there is no internal optimization, the prediction time of the Kriging model is saved. Experimental results on two real-world circuits demonstrate that compared with the state-of-the-art multi-objective Bayesian optimization, our method can reduce the training time of Kriging model by 95% and the prediction time by 99.7% without surrendering optimization results. Compared with NSGA-II and MOEA/D, the proposed method can achieve up to 10X speed up in terms of the total optimization time while achieving better results.