Formal Techniques to Verify Functionality of Digital Memory Decoder

Abstract

This research study discusses about the formal property verification of physical digital memory decoders, which is considered as a crucial component of most digital integrated circuits. This study presents a formal verification technique suitable for verifying the correctness of physical layer digital memory decoders. The proposed method is based on a formal language for describing the system, which is then verified using Formal Property Verification (FPV) techniques. The results of the verification process are discussed and compared with those obtained using traditional simulation techniques.