{"title":"A Clockless Computing System Based on the Static Dataflow Paradigm","authors":"L. Verdoscia, R. Vaccaro, R. Giorgi","doi":"10.1109/DFM.2014.10","DOIUrl":null,"url":null,"abstract":"The ambitious challenges posed by next exascale computing systems may require a critical re-examination of both architecture design and consolidated wisdom in terms of programming style and execution model, because such systems are expected to be constituted by thousands of processors with thousands of cores per chip. But how to build exascale architectures remains an open question.This paper presents a novel computing system based on a configurable architecture and a static dataflow execution model. We assume that the basic computational unit is constituted by a dataflow graph. Each processing node is constituted by an ad hoc kernel processor - designed to manage and schedule dataflow graphs, and a manycore dataflow execution engine - designed to execute such dataflow graphs.The main components of the dataflow execution engine are the Dataflow Actor Cores (DACs), which are small, identical and configurable. The major contributions of this paper are: i) the introduction of a machine language (named D#) which represents the low-level static configuration information of the system; ii) the introduction of a self-scheduled clockless mechanism to start operations on the presence of validity tokens only; iii) a design that avoids the need of temporary storage for tokens on the links of the DACs.Our preliminary tests on FPGA-based hardware show the feasibility of this approach.","PeriodicalId":183526,"journal":{"name":"2014 Fourth Workshop on Data-Flow Execution Models for Extreme Scale Computing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Fourth Workshop on Data-Flow Execution Models for Extreme Scale Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFM.2014.10","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
Abstract
The ambitious challenges posed by next exascale computing systems may require a critical re-examination of both architecture design and consolidated wisdom in terms of programming style and execution model, because such systems are expected to be constituted by thousands of processors with thousands of cores per chip. But how to build exascale architectures remains an open question.This paper presents a novel computing system based on a configurable architecture and a static dataflow execution model. We assume that the basic computational unit is constituted by a dataflow graph. Each processing node is constituted by an ad hoc kernel processor - designed to manage and schedule dataflow graphs, and a manycore dataflow execution engine - designed to execute such dataflow graphs.The main components of the dataflow execution engine are the Dataflow Actor Cores (DACs), which are small, identical and configurable. The major contributions of this paper are: i) the introduction of a machine language (named D#) which represents the low-level static configuration information of the system; ii) the introduction of a self-scheduled clockless mechanism to start operations on the presence of validity tokens only; iii) a design that avoids the need of temporary storage for tokens on the links of the DACs.Our preliminary tests on FPGA-based hardware show the feasibility of this approach.
下一个百亿亿次计算系统所带来的雄心勃勃的挑战可能需要对架构设计和编程风格和执行模型方面的整合智慧进行批判性的重新检查,因为这样的系统预计将由数千个处理器组成,每个芯片有数千个内核。但如何构建百亿亿级架构仍然是一个悬而未决的问题。本文提出了一种基于可配置架构和静态数据流执行模型的新型计算系统。我们假设基本计算单元由数据流图构成。每个处理节点都由一个专门的内核处理器(设计用于管理和调度数据流图)和一个多核数据流执行引擎(设计用于执行此类数据流图)组成。数据流执行引擎的主要组件是数据流Actor内核(dataflow Actor Cores, dac),它们很小、相同且可配置。本文的主要贡献有:i)引入了一种机器语言(命名为d#),它表示系统的底层静态配置信息;Ii)引入自调度无时钟机制,仅在存在有效令牌时启动操作;iii)避免在dac链路上临时存储令牌的设计。我们在基于fpga的硬件上的初步测试表明了这种方法的可行性。