{"title":"A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution","authors":"Erez Zolkov, Roy Weiss, A. Madjar, E. Cohen","doi":"10.1109/EuMIC48047.2021.00061","DOIUrl":null,"url":null,"abstract":"Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EuMIC48047.2021.00061","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.