A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution

Erez Zolkov, Roy Weiss, A. Madjar, E. Cohen
{"title":"A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2 ps Delay Resolution","authors":"Erez Zolkov, Roy Weiss, A. Madjar, E. Cohen","doi":"10.1109/EuMIC48047.2021.00061","DOIUrl":null,"url":null,"abstract":"Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.","PeriodicalId":371692,"journal":{"name":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 15th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EuMIC48047.2021.00061","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

Integrated true time delay cells are usually large in size, and have high relative delay variation. Here, the true time delay N-path topology is explored, where the signal is under-sampled with a number of parallel S/H circuits, and reconstructed and summed after a given time delay. The proposed circuit provides minimum resolution in time delay, while requiring relatively small area and power. The effect of the true time delay is analyzed with a linear periodic time-variant mathematical model, and is verified through measurements. Measurements of 65-nm CMOS chip implementation show up to 2 ns delay for bandwidth of 400 MHz, with maximum delay variation over frequency of 14 ps, delay resolution of 2 ps and power consumption of 9.6 mW.
实现2ps延迟分辨率的低功耗65nm CMOS真时间延迟n路电路
集成真延时单元通常体积较大,相对延时变化较大。在这里,我们探索了真正的时间延迟n路径拓扑,其中信号用多个并行S/H电路进行欠采样,并在给定的时间延迟后重构和求和。该电路提供了最小的时间延迟分辨率,同时需要相对较小的面积和功率。利用线性周期时变数学模型分析了真时延的影响,并通过实测进行了验证。65纳米CMOS芯片实现的测量结果显示,在400 MHz带宽下,延迟可达2 ns,频率上的最大延迟变化为14 ps,延迟分辨率为2 ps,功耗为9.6 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信