Associative memory designs for VLSI implementation

Abstract

The author proposes systolic architectures for associative memories, resulting in systems whose performance parameters are realistically independent of size for long sequences of operations with proper optimization of instruction sequencing. The designs are based on well-known principles of pipelining and systolic operation using a collection of small building-block associative memories. Several alternative organizations, from a simple linear array to higher dimensional meshes and trees, are examined and evaluated with respect to cost and performance. The proposed architectures should lead to practical VLSI realizations of large associative memories, which would be impossible to implement under the 'operand-broadcasting' and 'reduction-by-wired-logic' paradigms.<>