A weight-adjustable hardware accelerator board for DTCNN implementation and application

Abstract

A new method which uses only comparison and matching circuits to implement the neural net is introduced. The digital accelerator board combined with FPGA for simulating the behavior of discrete-time cellular neurons is presented in this paper. Via host computer the connected-weights can be modified in the hardware nearly arbitrarily. The network can realize various functions if the weights satisfy some conditions. The experiments show that the computation speed exceeds software implementation by 70-1000 limes. Finally, an application of feature extraction on handwritten characters recognition system shows the efficiency of the hardware with low cost.