Heterogenous Integration of Silicon Ion Trap and Glass Interposer for Scalable Quantum Computing Enabled by TSV, Micro-bumps and RDL

Abstract

In this work, we report the heterogenous integration of ion trap on silicon assembled on glass interposer, where TSV, micro-bumps and redistribution layer are implemented and allow for ion trap design with significantly high flexibility. CMOS-compatible back-end-of-line process is employed on 300 mm silicon/glass wafer platform. Due to the incorporation of TSVs into ion trap design, the footprint of ion trap is reduced. Correspondingly, low parasitic capacitance (3 pF) and RF loss (insertion loss of −0.1 dB at frequency of 50 MHz) are achieved, presenting significant improvement than conventional trap that uses wire bonding as interconnections. The trap with reduced footprint also enables small-beam laser addressing. The obtained ion lifetime and heating rate are comparable with traps of similar dimension that operated in room temperature. Two solutions to mitigate trap heating issue are proposed. This heterogenous integrated ion trap is an important building block for scalable quantum information processing based on ion trap device.