K. S. Kumar, S. Raghavendran, C. Das, A. Kirubakaran
{"title":"Novel Single-Phase Packed U-Cell based Symmetrical Multilevel Inverters","authors":"K. S. Kumar, S. Raghavendran, C. Das, A. Kirubakaran","doi":"10.1109/ICPC2T53885.2022.9777047","DOIUrl":null,"url":null,"abstract":"This paper presents a packed U-Cell based symmetrical multilevel inverters for grid-connected Photovoltaic (PV) systems. The proposed MLI can raise the number of levels in the output voltage with reduced power electronic devices compared with the popular MLI structures. The level-shifted sinusoidal pulse width modulation technique is employed to generate the triggering pulses. In addition, the proposed MLI has the ability to operate during the non-unity power factor conditions without any limitations. Furthermore, the proposed topologies are tested for 9-Level generation under different loading conditions. Moreover, a comparison with the modern MLI topologies is presented in terms of device count to show the merits of the proposed MLI. MATLAB/Simulink toolbox is used to validate the performance of the proposed MLI under different loading conditions.","PeriodicalId":283298,"journal":{"name":"2022 Second International Conference on Power, Control and Computing Technologies (ICPC2T)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 Second International Conference on Power, Control and Computing Technologies (ICPC2T)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPC2T53885.2022.9777047","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a packed U-Cell based symmetrical multilevel inverters for grid-connected Photovoltaic (PV) systems. The proposed MLI can raise the number of levels in the output voltage with reduced power electronic devices compared with the popular MLI structures. The level-shifted sinusoidal pulse width modulation technique is employed to generate the triggering pulses. In addition, the proposed MLI has the ability to operate during the non-unity power factor conditions without any limitations. Furthermore, the proposed topologies are tested for 9-Level generation under different loading conditions. Moreover, a comparison with the modern MLI topologies is presented in terms of device count to show the merits of the proposed MLI. MATLAB/Simulink toolbox is used to validate the performance of the proposed MLI under different loading conditions.