Efficient memory performance for multi - issue processors

Abstract

The effect of memory hierarchy on the overall performance of multi-issue modem Processors (superscalar processor) depends on multiple interact approaches . This performance is more sensitive to the cache organizations and its trade offs. This paper evaluates the performance impact of memory configuration on modem superscalar processors by investigating the use of extra buffers and external queues between pipelines, for the out-of-order hardware architecture with bigger sizes. For a combined effect on the performance improvement, an experimental framework has been suggested using SPEC benchmarks and SimpleScalar simulator. Effects of increasing DLl and ILl cache sizes, 'higher associativity, larger block size, increasing the RUU size and increasing the IFQ on IPC and the cache miss ratio have been illustrated. The objective is to achieve a performance level close to that of an ideal cache with low hardware cost and suitable for most recent superscalar techniques.