FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters

Abstract

Field programmable gate arrays (FPGAs) have been adopted in various fields, due to the design flexibility and customizability. Different applications have different requirements in performance, hardware resources and cost, leading to demands of diverse FPGA architectures. Delay is an important metric to evaluate different alternatives during FPGA architecture development. The existing analytical delay models for FPGAs mainly consider the logical architecture parameters. However, the variations of transistor-level parameters, Vdd and Vt, also have great influences on delay under the development trend of low-power design and deep sub-micron technology. To explore various design options at the early design stage and provide transistor-level accuracy, FPGA delay model considering Vdd and Vt is necessary. In this paper, an analytical model containing structural parameters of logic blocks and routing blocks as well as Vdd and Vt, is built to estimate the FPGA critical path delay.