A New Fast and Side-Channel Resistant AES Hardware Architecture

Abstract

In this paper we present a novel architecture for a high-speed AES crypto core which is resistant against first-order side channel attacks; our design combines Boolean masking techniques, logic obfuscation applied to a composite-fields Sbox implementation, and interleaved computations. This approach reaches a remarkable trade-off between size, performance and need for randomness, showing to be competitive against designs based on threshold approaches and automated masking. We conduct simulation-based and FPGA-based security evaluations, which are shown to corroborate our security objectives.