A fully-differential symmetrical OTA-based rail-to-rail switched buffer

Abstract

A CMOS low-voltage low-power switched OTA, optimized for its buffer configuration, suitable for both many portable applications and as input stage in digital architectures, is here presented. The circuit is a fully differential topology based on a symmetrical OTA featuring a rail-to-rail input and a reduced CMRR. It has been designed in a standard CMOS 0.35 mum technology and operates at 2V single supply voltage, showing a maximum power consumption of about 560 muW. Simulation results have confirmed the validity of the proposed architecture and have shown a -85dB THD for 100 kHz clock frequency, when a single tone input with lVpp amplitude at 10 kHz is applied.