Performance of parallel logic event simulation on PC-cluster

T. Le, J. Rejeb
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引用次数: 1

Abstract

PC-cluster is becoming more and more popular in many scientific and engineering applications, but not in electronic design areas. One of the reasons that parallel simulations have not been popularized is due to the high cost of frequent communications of small messages. Several simulation techniques have been aggressively studied and developed in the past ten years. These studies mostly focused on parallel VHDL simulation. In this paper, we show the effects of PC-cluster communication latencies on the performance of parallel discrete event simulation. We performed the experiments with two equivalent 8-node PC-cluster systems, one with regular Ethernet cards and one with Myrinet network cards. In order to study the effects of communication costs on the overall performance of parallel simulation algorithms, our study concentrates on fundamental techniques of discrete parallel event simulation scheme. The simulation processes are synchronized by the time warp mechanism and the problem domain is partitioned for best parallel performance. The speedup results show that although current PC-cluster technology is ready for parallel logic simulator, even for high-demanding communication applications, new algorithms that can avoid or minimize the computational rolling-back must be developed in order to catch up the rapid advancement of microprocessor technologies.
并行逻辑事件仿真在pc集群上的性能研究
pc机集群在许多科学和工程应用中越来越受欢迎,但在电子设计领域却没有得到广泛应用。并行仿真尚未普及的原因之一是小消息频繁通信的高成本。在过去的十年里,一些模拟技术得到了积极的研究和发展。这些研究主要集中在并行VHDL仿真上。在本文中,我们展示了pc -集群通信延迟对并行离散事件模拟性能的影响。我们在两个等效的8节点pc集群系统上进行了实验,一个使用常规以太网卡,另一个使用Myrinet网卡。为了研究通信成本对并行仿真算法整体性能的影响,本文主要研究离散并行事件仿真方案的基本技术。采用时间扭曲机制对仿真过程进行同步,并对问题域进行划分以获得最佳并行性能。加速结果表明,尽管目前的pc集群技术已经为并行逻辑模拟器做好了准备,即使对于高要求的通信应用,为了赶上微处理器技术的快速发展,必须开发新的算法来避免或最小化计算回滚。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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