A high-performance error concealment processor for video decoder

Abstract

Recently, the video decoding players, such as DVD, VCD, have widely used. However, the image has large distortions as the decoding bit stream from damaged disks. In this study, we develop an error concealment processor for real-time video decoding systems. First, an efficiency algorithm is advised for error concealment with adaptations of the spatial interpolation and the temporal prediction. Based on the adaptive algorithm, real-time VLSI architecture is developed using cell-based design. The complex processing schedule for the error concealment processor is planned as integrated to video decoding systems. The chip occupies one line-buffer and about 27k logic gates using TSMC 0.35/spl mu/m process. The throughput rate of this error concealment chip can achieve about 50M pixels per second using about 9mm/sup 2/ silicon area.