Reducing inter-configuration memory usage and performance improvement in reconfigurable computing systems

Abstract

For running subsequent configurations in a reconfigurable computing system intermediate data must transfer between them. Reducing memory usage overhead can result in reduction in the array size and the number of input/output pins. In this paper, a new iterative design flow is proposed which integrates the synthesis and physical design aspects for performing a static compilation process. A new temporal partitioning algorithm for partitioning and scheduling is proposed, which tries to increase similarity of subsequent configurations in such a way that the reconfiguration time on a partially reconfigurable hardware decreases. In addition, we perform an iterative physical design process based on similar configurations produced in the previous stage. A modified algorithm improves our prior temporal partitioning algorithm, which usually had large overhead of memory usage and the number of input/output pins. This new approach performs partitioning in depth and tries to minimize the memory and 10 requirements.