A 0.8V Chopper Amplifier with 600mVpp Tolerance to Power-Line Interference for Neural Signal Acquisition

Abstract

This paper proposes a chopper amplifier working under 0.8V supply voltage implemented in TSMC 0.18um CMOS technology, enabling a 2.02uW per channel, while preserving a good tolerance of power-line interference (PLI) up to 600mVpp, a THD of -65.5dB, and high robustness against the PVT, by implementing a common-mode cancellation loop (CMCL) based on a feedback loop, a new offset cancellation loop (OCL), and a new very-lower transconductance (VLT) OTA. The measured mid-band gain is 43.3dB with a high-pass cut-off of 1.2Hz and a low-pass cut-off of 17kHz. The measured integrated noise is 0.75uVrms and 4.8uVrms in the frequency band of 1 − 200Hz and 0.2 − 17kHz, respectively, leading to a power efficiency factor (PEF) of 8.4 and 4.05.