A. Benveniste, P. Bournai, T. Gautier, M. L. Borgne, P. Guernic, H. Marchand
{"title":"The SIGNAL declarative synchronous language: controller synthesis and systems/architecture design","authors":"A. Benveniste, P. Bournai, T. Gautier, M. L. Borgne, P. Guernic, H. Marchand","doi":"10.1109/CDC.2001.980328","DOIUrl":null,"url":null,"abstract":"Harel and Pnueli showed (1985) that dynamical systems are an essential in the area of computer science. In this context they are called reactive systems. Synchronous languages have been proposed as a paradigm to deal with reactive systems and develop tools for them. In this paper we introduce synchronous programming paradigm via the notion of multiclock dynamical systems and illustrate it via the SIGNAL language. We give an outline of controller synthesis in SIGNAL, and system/architecture design.","PeriodicalId":131411,"journal":{"name":"Proceedings of the 40th IEEE Conference on Decision and Control (Cat. No.01CH37228)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 40th IEEE Conference on Decision and Control (Cat. No.01CH37228)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CDC.2001.980328","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
Harel and Pnueli showed (1985) that dynamical systems are an essential in the area of computer science. In this context they are called reactive systems. Synchronous languages have been proposed as a paradigm to deal with reactive systems and develop tools for them. In this paper we introduce synchronous programming paradigm via the notion of multiclock dynamical systems and illustrate it via the SIGNAL language. We give an outline of controller synthesis in SIGNAL, and system/architecture design.