Implementing Globally Asynchronous Locally Synchronous processor pipeline on commercial synchronous FPGAs

Abstract

In this paper a Globally-Asynchronous Locally-Synchronous (GALS) pipelined processor is implemented on synchronous commercial FPGAs. A simple pipelined accumulator-based processor is implemented as an example for a pipelined processor with varying stages' delays. A novel port controller is designed to ensure the proper operation of the pipeline under any distribution of stage delays. The results show that the GALS approach increase the pipeline throughput by 21% and reduces the power consumption by 26.8%.