Triple-threshold-voltage 9-transistor SRAM cell for data stability and energy-efficiency at ultra-low power supply voltages

Abstract

Supply voltage scaling is a commonly used technique for saving energy in microprocessors. The scalability of power supply voltage is limited by the data stability and write ability requirements of SRAM cells in memory cache. Noise margins of memory cells shrink, thereby degrading reliability and causing failure at lower power supply voltages. A triple-threshold-voltage nine-transistor SRAM cell that is capable of reliable operation at ultra-low power supply voltage levels down to 390mV is presented in this paper. While offering comparable or higher data stability, the tri-Vt 9T SRAM array lowers the leakage power consumption, energy per read cycle, and energy per write cycle by up to 94.5%, 22.8%, and 34.5%, respectively, as compared to the conventional 6T SRAM arrays that operate at the nominal VDD = 1.2V in a TSMC 65nm CMOS technology.