Practical considerations of read-out circuits for passive, multi-level ReRAM arrays

Abstract

ReRAM is emerging as a potential replacement candidate for post-Moore flash memory, while the sneak-path problem may hinder the possible applications in multi-level storages. The paper presents two proper sneak-path mitigation bias schemes (PD-read scheme and TIA-read scheme) for the multi-level read-out applications, and focus on the understanding of the effect of ADC misread that limits the multi-level read-out performance. The detail theoretical deduction of the read-out performance degradation induced by the ADC misread is present. A verified hardware system is built. The experimental results show that both the read-out schemes can measure precisely the resistance of linear resistors ranging from IΩ to 1MΩ. TIA — read scheme is more tolerant for the ADC misread than PD-read scheme, thus be more suitable as the multi-level read-out scheme.