A data-pattern independent clock and data recovery IC with a two-mode phase comparator

Abstract

Clock and data recovery (CDR) with a novel two-mode phase comparator (PC) is proposed. The 10-Gbit/s CDR IC stably operates both for consecutive identical digits (CIDs) and for data transition density variations. This advancement is achieved by the novel two-mode PC, which enables us to optimize phase-locked loop parameters for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 ps/sub pp/ for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. They also show that the jitter transfer and jitter tolerance are not affected by the data transition density factors between 1/8 and 1/2.