D. Sucharitha, N. Prudhvi Raj, R. Sravya, Sudheer Raja Venishetty
{"title":"GDI Logic Based Design of Hamming-Code Encoder and Decoder for Error Free Data Communication","authors":"D. Sucharitha, N. Prudhvi Raj, R. Sravya, Sudheer Raja Venishetty","doi":"10.1109/ICCMC.2019.8819665","DOIUrl":null,"url":null,"abstract":"In this paper, Hamming code encoder and decoder circuit is designed based on Gate Diffusion Input (GDI) logic to achieve error free transmission and reception in digital data communication. GDI logic is a new technique used for designing low power VLSI circuits. This technique provides better trade-off between power, delay and area compared to other logic styles existing in the literature, while maintaining low complexity of the circuit. Hamming code encoder and decoder circuit architectures are developed using GDI technique and are simulated in gpdk 130 nm technology using Mentor Graphics® EDA tool. The advantages of GDI technique is reported in this paper in comparison to architectures developed using CMOS logic styles.","PeriodicalId":232624,"journal":{"name":"2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCMC.2019.8819665","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, Hamming code encoder and decoder circuit is designed based on Gate Diffusion Input (GDI) logic to achieve error free transmission and reception in digital data communication. GDI logic is a new technique used for designing low power VLSI circuits. This technique provides better trade-off between power, delay and area compared to other logic styles existing in the literature, while maintaining low complexity of the circuit. Hamming code encoder and decoder circuit architectures are developed using GDI technique and are simulated in gpdk 130 nm technology using Mentor Graphics® EDA tool. The advantages of GDI technique is reported in this paper in comparison to architectures developed using CMOS logic styles.