Hardware Support for Efficient Sparse Matrix Vector Multiplication

Abstract

Sparse matrix vector multiplication (SpMxV) is a core operation in many engineering, scientific and financial applications. Due to the sparse nature of the underlying matrices, irregular memory access patterns and short row lengths often slow down the performance significantly. Past implementations of SpMxV have been reported to be run at 10% or less of the machine's peak capability. In this paper we present a novel hardware support called distTree for efficient SpMxV. It is shown that replacing the column indices of sparse matrices with extra hardware is achievable and yields an average speedup by a factor of two for the suite of benchmarks used. The matrix data set for the distTree is approximately 30% less than that for conventional CSR algorithms so that distTree is beneficial in terms of not only performance but also memory usage. Thorough analysis is done by looking at the correlation between the performance speedups and various matrices properties.