A buffer-space allocation approach for application-specific Network-on-Chip

Abstract

Rapid advances in technology and design tools enabled today engineers to design system-on-chip containing large number of cores. These systems have limited resources and should be implemented with very little silicon area overhead. Several studies have demonstrated that buffers inside switches of the on-chip interconnect take a significant portion of the system silicon area that can affects the performance and the energy consumption. Therefore, their size should be carefully customized to match communication patterns of a target application. In this paper, a compartmental Fluid-flow based modeling approach is presented to allocate required resource for each buffer based on the application traffic pattern. Simulations are conducted and preliminary results are reported to show the efficiency of the Fluid-flow based modeling method for a buffer space allocation.