Partitioning Algorithms for a Class of Application Specific Multiprocessor Architectures

Abstract

We consider the problem of partitioning coarse grain signal flow graphs for execution on a class of hi erarc hical ly structured, heterogeneous mu12 iprocessor architectures tailored to match the characteristics of a specific application (e.g., acoustic beamforming), or a specific domain (e.g., radar signal processing). This is achieved by utilizing the desired mix of processing element types, e.g., ASICs, DSPs, generic processors, etc. We propose two heuristics and describe the experimental results of applying both heuristics to a set of generated flow graphs. The performance of these heuristics is also compared to that of an adaptive variant of simulated annealing[l].