Behavioral modeling of a SONET/SDH transceiver using HDLA

Abstract

In order to reduce the number of design iteration for complex mixed signal telecommunication IC's, verification through full chip simulation is a must. The objective is to verify connectivity and functionality for the whole chip including the interface between analog and digital blocks. Efficient top level simulation required the use of a mixed mode (Analog and Digital) simulator. In addition, in order to accomplish this task, behavioral models of all the system building blocks of the design were developed and used to replace the transistor level sub-circuit description. The design sub-blocks were modeled in HDLA.