Shuqin Wan, Zhenhai Chen, Zongguang Yu, Songren Huang, H. Ji
{"title":"An embedded 14-bit 800MS/s DAC for direct digital frequency synthesizer in 0.18-μm CMOS","authors":"Shuqin Wan, Zhenhai Chen, Zongguang Yu, Songren Huang, H. Ji","doi":"10.1109/ASEMD.2009.5306681","DOIUrl":null,"url":null,"abstract":"An embedded 14-bit 1-GS/s digital-to-analog converter for Direct Digital Frequency Synthesizer (DDFS) application is presented. The DAC is implemented using a segmented current-steering architecture, with the top 6bits and the remaining 8 bits. The output stage of dual return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range (SFDR). The DAC core is fabricated in a 1P6M 0.18 μm standard CMOS technology occupies a die area of only 1.6 × 1.5 mm2. The measured differential nonlinearity lies between −0.8 LSB and 0.3LSB, integral nonlinearity lies between −1.5LSB and 1LSB. And the SFDR is 76.47 dB for 80 MHz output at 0.8GHz sampling clock rate.","PeriodicalId":354649,"journal":{"name":"2009 International Conference on Applied Superconductivity and Electromagnetic Devices","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Applied Superconductivity and Electromagnetic Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASEMD.2009.5306681","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
An embedded 14-bit 1-GS/s digital-to-analog converter for Direct Digital Frequency Synthesizer (DDFS) application is presented. The DAC is implemented using a segmented current-steering architecture, with the top 6bits and the remaining 8 bits. The output stage of dual return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range (SFDR). The DAC core is fabricated in a 1P6M 0.18 μm standard CMOS technology occupies a die area of only 1.6 × 1.5 mm2. The measured differential nonlinearity lies between −0.8 LSB and 0.3LSB, integral nonlinearity lies between −1.5LSB and 1LSB. And the SFDR is 76.47 dB for 80 MHz output at 0.8GHz sampling clock rate.