Ion-implanted GaAs JFETs with f/sub t/>45 GHz for low-power electronics

J. Zolper, A. Baca, M. Sherwin, V. Hietala, J. Shul
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Abstract

GaAs Junction Field Effect Transistors (JFETs) are reported with gate lengths down to 0.3 /spl mu/m. The structure is fully self-aligned and employs all ion implantation doping. p/sup +/-gate regions are formed with either Zn or Cd implants along with a P co-implantation to reduce diffusion. The source and drain implants are engineered with Si or SiF implants to minimize short channel effects. 0.3 /spl mu/m gate length JFETs are demonstrated with a subthreshold slope of 110 mV/decade along with an intrinsic unity current gain cutoff frequency as high as 52 GHz.
用于低功耗电子器件的f/sub />45 GHz离子注入GaAs jfet
据报道,GaAs结场效应晶体管(jfet)的栅极长度低至0.3 /spl mu/m。该结构是完全自对准的,采用全离子注入掺杂。p/sup +/-栅极区是由Zn或Cd注入和p共注入形成的,以减少扩散。源极和漏极植入物采用Si或SiF植入物设计,以尽量减少短通道效应。0.3 /spl mu/m栅极长度的jfet的亚阈值斜率为110 mV/decade,固有的单位电流增益截止频率高达52 GHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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