Stability analysis and measurement of RC and RL digital non-Foster circuits with latency

Abstract

Stability analysis and measurements are presented for negative capacitance and negative inductance designs of digital non-Foster circuits that include a series resistance and model the effects of latency. Such digital non-Foster circuits provide a new important alternative to analog non-Foster circuits, with potential to address stability and performance issues in important non-Foster application areas such as metamaterials, acoustic cloaking, and electrically-small antennas. The proposed approach includes a resistive component in the signal processing of digital non-Foster RC and RL circuits to help control stability and to mitigate parasitic resistance, and also includes latency effects associated with computation and conversion time. Analysis, simulation, and measured results confirm the desired non-Foster impedances, and show useful regions of stability as a function of resistance and latency.