11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS

Abstract

Several 400G Ethernet standards (e.g. 400G-DR4/FR4) have been developed to address the rapid increase in interconnect BW demand created by data-centric computing [1]. Low-cost100Gb/s PAM-4 optical transceivers are critical to spur their adoption in high volume by data centers. While low-cost integrated silicon-photonic 100Gb/s PAM-4 transmitters have been demonstrated recently, the electronics in current receiver solutions is more disaggregated. They typically employ a standalone BiCMOS TIA 1C followed by a 100G PAM-4 (ADC+DSP)-based SerDes 1C (designed to equalize high-loss electrical channels), which results in higher power dissipation and package cost. To address these drawbacks, we present a 100Gb/s PAM-4 optical RX with a single-chip Solution integrating all 0f the RX electronics in a bulk CMOS process. While standalone l00Gb/s PAM-4 CMOS linear TIAs have been shown in prior work [2], [3], their integration with subsequent SerDes has not yet been demonstrated.