Application of circuit-level hot-carrier reliability simulation to memory design

Abstract

We have applied hot-carrier circuit-level simulation to entire circuits of a few thousand to over 12 K transistors using a simple but accurate degradation model for reliability verification of actual memory products. Previous published applications were small scale (few tens of transistors or individual circuit blocks) or for experimental purposes. By applying simulation to entire circuits, areas with worst degradation are not missed due to simulating only certain circuit blocks. Varying degradation depending upon actual products make accurate total-circuit simulation a crucial part of the early design process as technology advances into the deep sub-micron high clock rate regime.