A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS

Abstract

A single-loop full-rate bang-bang CDR without the reference and separate frequency detector (FD) is reported. Its phase detector innovates a strobe-point selection scheme and a hybrid control circuit to automate and accelerate the frequency acquisition over a wide frequency range. Prototyped in 28nm CMOS, our CDR achieves a 23-to-29Gb/s capture range of four-level pulse amplitude modulation (PAM-4) data. The acquisition speed [8.2(Gb/s)/µs], die area (0.0285mm2) and energy efficiency (0.68pJ/bit) compare favorably with the prior art.