A Transient-Enhanced Capacitorless LDO Regulator with improved Error Amplifier

Abstract

This paper presents a modified folded cascode error amplifier of low dropout (LDO) regulator and a slew-rate enhancement circuit to minimize compensation capacitance and improve transient response. The proposed error amplifier eliminates the tradeoffs between small and large slew-rate that is imposed by the tail-current in conventional error amplifier design. The design is implemented in a standard UMC 0.18 ìm standard CMOS process. Simulation results show that, the LDO regulator consumes a quiescent current of 49.64μA only with a total power consumption of .079mW. It regulates the output voltage at 1.4v from 1.6-1.8v supply. The overshoot/undershoot in the output voltage under the extreme load transients are 220.7mV/280.26mV for load current range of 0 to 100mA. The line regulation is 1.244mV/V at 1.8V, load regulation is 40.6mV/A. This circuit finds its beneficial behavior for chip-level power management units requiring high-area efficiency as compensation capacitors are avoided.