IMPACT: an architectural framework for multiple-instruction-issue processors

Abstract

The performance of multiple-instruction-issue processors can be severely limited by the com piler’s ability to generate efficient code for concurrent hardware. In the IM P A C T project, we have developed IM P AC T-I, a highly optimizing C compiler to exploit instruction level con currency. The optimization capabilities of the IM P A C T -I C compiler is summarized in this paper. Using the IM P AC T-I C compiler, we ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The multiple-instruction-issue processors have achieved solid speedup over a high-performance single instruction-issue processor. To address architecture design issues, we ran experiments to charaterize the engineering tradeoffs such as the code scheduling model, the instruction issue rate, the memory load latency, and the function unit resource limitations. Based on the experimental results, we propose the IM P A C T Architectural Framework, a set of architectural features that best support the IM P A C T -I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediate compilation support from the IM P A C T -I C compiler.