CAD tool for parameterized FPGA based FFT architectures

Abstract

This paper describes a software tool for simulating and generating fully parallel generic VHDL representations of Fast Fourier Transforms. A comparison between parallel-parallel and serial-parallel butterflies is performed with emphasis on maximizing speed and/or minimizing FPGA area. Comparisons of the software tool to other VHDL/Verilog generators, namely CoreGen and SPIRAL, are also explored.