Symbol error correcting codes for memory applications

Abstract

Symbol error correcting codes have been used for fault tolerance in computer memory subsystems configured in b-bits-per-chip. This paper presents algorithms for designing the parity check matrices of symbol error correcting codes to reduce circuit count and the circuit time delay. It presents a technique for formulating the parity check matrices for modular implementation. It also presents codes that use a smaller number of circuits and require a shorter circuit delay time than other known codes. These results are useful for practical design of symbol error correcting codes.