An Overview of On-Chip ESD Protection in Modern Deep Sub-Micron CMOS Technology

Abstract

Electrostatic discharge (ESD) protection is a field with increasing importance in the era of sub-10-nm technology nodes. Device scaling comes at a price of thinner gate dielectrics and metallization layers, leakage currents management issues, device-to-die area ratio efficiency, etc. On the other hand, CMOS technology is steadily gaining traction in mixed-signal and RF applications which impose their own set of requirements. Parasitic capacitance and latch-up immunity are the major concerns for an ESD device used in high-speed circuits. This paper provides an in-dept systematic overview of optimization methods employed to meet the latest parameter requirements created by emerging sub-micron integrated circuits designs.