System-Level Evaluation of Video Processing System Using SimpleScalar-Based Multi-core Processor Simulator

Zidong Du, Bingbing Xia, F. Qiao, Huazhong Yang
{"title":"System-Level Evaluation of Video Processing System Using SimpleScalar-Based Multi-core Processor Simulator","authors":"Zidong Du, Bingbing Xia, F. Qiao, Huazhong Yang","doi":"10.1109/ISADS.2011.34","DOIUrl":null,"url":null,"abstract":"Multi-core processor Simulation Platform is always a very important tool in modern multi-core processor design for the system-level design and evaluation. In this paper, a multi-core processor simulator is proposed by modifying Simple Scalar v3.0to simulate parallelized multi-core programs. Shared memory is used for the communication between different cores, which is the communication network among several different parts of the parallelized program separately. Two simulators are designed for different kinds of usage, one for functional simulation and the other for the simulation of the system with two-level cache. The mismatch of such simulator is less than 10% on average, and the presented simulator is used to evaluate the high-performance video processing systems.","PeriodicalId":221833,"journal":{"name":"2011 Tenth International Symposium on Autonomous Decentralized Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Tenth International Symposium on Autonomous Decentralized Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISADS.2011.34","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

Multi-core processor Simulation Platform is always a very important tool in modern multi-core processor design for the system-level design and evaluation. In this paper, a multi-core processor simulator is proposed by modifying Simple Scalar v3.0to simulate parallelized multi-core programs. Shared memory is used for the communication between different cores, which is the communication network among several different parts of the parallelized program separately. Two simulators are designed for different kinds of usage, one for functional simulation and the other for the simulation of the system with two-level cache. The mismatch of such simulator is less than 10% on average, and the presented simulator is used to evaluate the high-performance video processing systems.
基于simplescalar的多核处理器模拟器视频处理系统的系统级评价
多核处理器仿真平台一直是现代多核处理器设计中进行系统级设计和评估的重要工具。本文通过对Simple Scalar v3.0的改进,提出了一个多核处理器模拟器来模拟并行化的多核程序。共享内存用于不同核之间的通信,这是并行化程序的几个不同部分之间的通信网络。设计了两种不同用途的仿真器,一种用于功能仿真,另一种用于两级缓存系统的仿真。该仿真器的平均失配小于10%,可用于高性能视频处理系统的评估。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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