A power-on reset with accurate hysteresis

Abstract

As the complexity of the digital circuit blocks continues to increase, a power-on reset, POR, circuit is needed to initialize the digital logic to the known state at the start-up. This paper represents a POR with thresholds that are insensitive to the rise time of the supply voltage. This is achieved by generating the POR pulse with a constant current reference circuit. Moreover, current mirroring is used to improve hysteresis. The designed POR has a quiescent current of 3.1 µA (VDD=3.6 V) and operates with supplies ranging from 3 V to 3.6 V. The area of the circuit is 109.9 µm × 106.65 µm and the chip was implemented with triple-well 0.35 µm HVCMOS process.