Performance Evaluation of Low-Voltage CMOS Switched-Capacitor Circuit

Abstract

Switched capacitor circuits play recently a vital role in numerous devices and applications. Switched capacitor circuits need to be designed accurately and optimized the circuit design parameters for a better performance. This is very challenging due to the compromise among different key factors such as power conversion efficiency, loading current and circuit size. In this work, Analytical optimization approach was implemented to optimize the switched capacitor charge pump circuit design with the load current. In this kind of circuit design, various parameters need to be considered for optimization such as voltage gain, output voltage ripple, output impedance, power conversion efficiency, and the circuit area. Here the analytical approach of optimization was applied to the conventional and bootstrapped methods switched capacitor charge pump circuits of five stages. For these kind of circuits, it is always required to obtain low consumption power, minimum generated charge, and small chip area. In this study, 0.18-µm CMOS technology was adopted with 2 V, 10 pF and 100MHz. The obtained results based on the proposed bootstrapped method showed that the circuit has better efficiency (68.5%) compared to (53 %) when using the conventional method. This could be very useful for many devices and applications.