Testing of VLSI CMOS System/390 processor at card and system level

Abstract

The authors describe the design for testability (DFT) and testing methodology for the S/390 processor being part of IBM's low-end ES/9000 systems. The design incorporates built-in pseudo-random pattern self test and the boundary scan technique. Self test permits the migration of tests generated for the component level to higher-level packages such as printed circuit boards and the system. Consequently, the expense for testing of higher-level packages has been drastically reduced and the card test equipment can be simplified. In addition, the applied strategy offers economical diagnostic capability.<>