G. Uvieghara, M. Kuo, J. Arceo, J. Cheung, J. Lee, X. Niu, R. Sankuratri, M. Severson, O. Arias, Y. Chang, S. King, K. Lai, Y. Tian, S. Varadarajan, J. Wang, K. Yen, L. Yuan, N. Chen, D. Hsu, D. Lisk, S. Khan, A. Fahim, C.L. Wang, J. DeJaco, Z. Mansour, M. Sani
{"title":"A highly-integrated 3G CDMA2000 1X cellular baseband chip with GSM/AMPS/GPS/Bluetooth/multimedia capabilities and ZIF RIF support","authors":"G. Uvieghara, M. Kuo, J. Arceo, J. Cheung, J. Lee, X. Niu, R. Sankuratri, M. Severson, O. Arias, Y. Chang, S. King, K. Lai, Y. Tian, S. Varadarajan, J. Wang, K. Yen, L. Yuan, N. Chen, D. Hsu, D. Lisk, S. Khan, A. Fahim, C.L. Wang, J. DeJaco, Z. Mansour, M. Sani","doi":"10.1109/ISSCC.2004.1332774","DOIUrl":null,"url":null,"abstract":"This paper presents a 3G CDMA2000 1X cellular-baseband chip, with GSM/AMPS/GPS/Bluetooth/multimedia capabilities, which uses an embedded ARM and two DSP processors. It is implemented with 27 M transistors in 46.9 mm/sup 2/ using a 130 nm dual-V/sub T/ low-power CMOS process and achieves a three to four times standby-time improvement by the selective use of footswitches.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
Abstract
This paper presents a 3G CDMA2000 1X cellular-baseband chip, with GSM/AMPS/GPS/Bluetooth/multimedia capabilities, which uses an embedded ARM and two DSP processors. It is implemented with 27 M transistors in 46.9 mm/sup 2/ using a 130 nm dual-V/sub T/ low-power CMOS process and achieves a three to four times standby-time improvement by the selective use of footswitches.