Investigation on novel comparator design

Abstract

This paper investigates four innovative comparators design and their performance. A Latch-type comparator comprising two cross-coupled inverters is altered for fast operation, with advantages of a high-impedance input, robustness against mismatch, and no static power consumption kept. A splendid technique is a low-power high-precision comparator with an offset scheme implemented on it, achieving a fast and robust offset convergence. The scheme barely introduces delay and mismatch and is designed with minimal extra power consumption and delay. A novel triple-Latch Feedforward (TLFF) fully Dynamic Comparator composed with three stage latches and a feedforward path is proposed to reduce the delay remarkably for large differential input. Another dynamic-bias comparator is designed and compared with prior study, saving the energy consumption considerably with given noise. However, it sacrifices the operation speed due to incomplete discharge. Considerations on the circuit design and performances of the above-mentioned comparators will be discussed in this paper.