A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface using novel eye-tracking method

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221160

T. Saito, H. Yamashita, F. Yuki, T. Baba, A. Koyama, M. Sonehara

引用次数: 2

Abstract

We developed a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Our unique approach of treating a sequential 16-bit incoming data as one unit achieved a fully digital "eye-tracking" DR circuit. Fabricated by 0.18-/spl mu/m SiGe-BiCMOS technology, the area of the DR circuit is 0.02-mm/sup 2//ch and its power consumption is 50 mW/ch at 1.8 V. The measured jitter tolerance at 2.5 Gb/s is 0.7 UI p-p, which satisfies the jitter specifications for the SFI-5.

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采用新颖的眼动追踪方法，为SFI-5接口设计了50mw /ch 2.5 gb /s/ch数据恢复电路

我们为SFI-5接口开发了2.5 gb /s/ch的数字数据恢复(DR)电路。我们将16位连续输入数据作为一个单元处理的独特方法实现了全数字“眼球追踪”DR电路。采用0.18-/spl mu/m SiGe-BiCMOS工艺制作，DR电路面积为0.02 mm/sup //ch, 1.8 V时功耗为50 mW/ch。测量到的2.5 Gb/s下的抖动容差为0.7 UI - p-p，满足SFI-5的抖动规格。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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